Method and structure of forming self-aligned rmg gate for vfet

ABSTRACT

An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers, each of the sidewall spacers having vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a temporary hard mask to pattern the SiN hard mask.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. patentapplication Ser. No. 15/212,755, filed Jul. 18, 2016, and entitled“METHOD AND STRUCTURE OF FORMING SELF-ALIGNED RMG GATE FOR VFET,” theentirety of which is hereby incorporated herein by reference.

TECHNICAL FIELD

This invention relates to vertical field effect transistors (VFET) andmore particularly to forming self-aligned replacement metal gatestherefor.

BACKGROUND INFORMATION

Currently, the fabrication of VFETs utilize a gate first fabricationtechnique. Gate first fabrication techniques refer to a situation wherethe gate is patterned prior to the annealing step used to activate thesource and drain. However, in gate last techniques, a dummy gate is usedto occupy the gate space during the annealing process and a replacementmetal gate is inserted into the dummy gate area after the anneal. Thegate last technique and the use of replacement metal gates avoids thedifficult thermal issues normally encountered with use of the gate firsttechnique.

Accordingly, it is desirable to provide a self-aligned replacement metalgate method and structure for forming self-aligned replacement metalgates for vertical field effect transistors to provide desired thermalcharacteristics and effective area scaling.

SUMMARY OF THE INVENTION

In accordance with one aspect of the invention, a method of providing afin structure is disclosed. The fin structure includes a fin withsacrificial material above and adjacent the fin, with the fin structurebeing above a substrate adjacent a source or drain. The method includesremoving a first portion of the sacrificial material above the fin toform an opening within the sacrificial material on top of the fin,forming a top source or drain within the opening on top of the fin,removing a second portion of the sacrificial material adjacent the topsource or drain, depositing a spacer above and adjacent the top sourceor drain, depositing a gate material above the spacer and below thespacer to the sides of the fin, and removing the gate material above thebottom portion of the spacer to form a self aligned gate around the finand a vertical field effect transistor.

The sacrificial material includes a first sacrificial material. A topportion of the first sacrificial material located above and adjacentsaid fin structure is removed to allow a remaining portion of the firstsacrificial material to remain adjacent said fin. A second sacrificialmaterial may be deposited above the remaining first sacrificial materialso that the sacrificial material includes a first sacrificial material,the second sacrificial material, and a hard mask on the top of the fin.

The first sacrificial material may be a thin oxide surrounding the finstructure and an amorphous silicon deposited on top of the thin oxide.The second sacrificial material may be an oxide. The removing of a firstportion of the sacrificial material above the fin to form an openingwithin the sacrificial material on top of the fin may include removingthe hard mask above or on top of said fin. The self-aligned contact(SAC) cap may be deposited above the top source or drain within theoxide. The method may also include removing the oxide prior todepositing a spacer above and adjacent the top source or drain. Also,removing a third portion of the sacrificial material adjacent the finmay include removing the amorphous silicon.

The method may further include removing the thin oxide, which may be asilicon oxide. The method may also include providing a bottom spacerabove the source or drain and substrate adjacent the fin. And, mayinclude depositing a high K dielectric material on the bottom spacer,where the spacer and the fin form an intermediate structure, andannealing the intermediate structure.

The method may also include depositing a work function metal as part ofthe gate material and a metal over the work function metal as part ofthe gate material.

Removing the gate material above the bottom portion of the spacer mayinclude removing the work function metal and the metal.

The method may further include removing annealed high K material abovethe spacer above and adjacent the top source or drain, depositing asecond lithography stack over the barrier stack, performing a secondlithography to pattern the at least one via opening, and etching to format least one via opening.

The method may also include providing multiple fin structures, multipletop sources or drains to form multiple vertical field effecttransistors. The fin structures may be parallel spaced with at least twovertical field effect transistors spaced apart and aligned along lengthsthereof and forming at least one additional gate connecting aligned onparallel spaced vertical field effect transistors.

In another aspect of the invention, the method includes providing a finstructure having a fin with a hard mask on top of the fin. The finstructure is above a substrate adjacent a source or drain. The methodincludes depositing one or more sacrificial materials above and alongsides of the fin structure, removing a top portion of the one or moresacrificial materials above a top of the fin to form an opening withinthe one or more sacrificial materials, forming a top source or drainwithin the opening on the top of said fin, removing a portion of the oneor more sacrificial materials above and adjacent the top source ordrain, depositing a spacer above the top source or drain, removingadditional portions of the one or more sacrificial materials surroundingsides of the fin, depositing gate material above the spacer and belowthe spacer to the sides of the fin, and removing the gate material abovethe bottom portion of the spacer to form a self aligned gate around thefin and vertical field effort transistor.

In another aspect of the invention, the invention includes anintermediate semiconductor structure having a fin structure. The finstructure includes a fin above a substrate adjacent a bottom source ordrain, a top source or drain located on the top of the fin, a spacerlocated above and surrounding the top source or drain and adjacent a topportion of the fin, a self-aligned gate structure located below the topspacer and above a bottom spacer located above said substrate and sourceor drain, and one or more work function layers located between thebottom spacer and side walls of the fin and top spacer.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

One or more aspects of the present invention are particularly pointedout and distinctly claimed as examples in the claims at the conclusionof the specification. The foregoing and other objects, features, andadvantages of the invention are apparent from the following detaileddescription taken in conjunction with the accompanying drawings inwhich:

FIG. 1A depicts a cross sectional view of a fin of negative channelfield-effect transistor device (nFET) including hardmask material whichmay be situated above and or included adjacent as a bottom spacer to thefin and can include a bottom source drain region and insulator region;

FIG. 1B depicts a cross sectional view of a fin of a positive channelfield-effect transistor device (pFET) including hardmask material whichmay be situated above and or included adjacent as a bottom to the finand can include a bottom source drain region and insulator region;

FIG. 2A depicts a cross sectional view of the structure of FIG. 1A afterapplication of a first sacrificial material which may be in the form ofa thin oxide surrounding said fin structure, and a second sacrificialmaterial which may be in the form of an amorphous silicon layer deposedupon the first sacrificial material;

FIG. 2B depicts a cross sectional view of the structure of FIG. 1B afterapplication of a first sacrificial material which may be in the form ofa thin oxide surrounding said fin structure, and a second sacrificialmaterial which may be in the form of an amorphous silicon layer deposedupon the first sacrificial material;

FIG. 3A depicts a cross sectional view of the structure of FIG. 2A afterremoving of a first portion of the first sacrificial material a firstportion of the second sacrificial material thereby exposing the hardmaskmaterial located above the fin;

FIG. 3B depicts a cross sectional view of the structure of FIG. 2B afterremoving of a first portion of the first sacrificial material a firstportion of the second sacrificial material thereby exposing the hardmaskmaterial located above the fin;

FIG. 4A depicts a cross sectional view of the structure of FIG. 3A afterthe recessing of a second portion of the first sacrificial furtherexposing the second sacrificial material;

FIG. 4B depicts a cross sectional view of the structure of FIG. 3B afterthe recessing of a second portion of the first sacrificial furtherexposing the second sacrificial material;

FIG. 5A depicts a cross sectional view of the structure of FIG. 4A afterapplication of a third sacrificial material which may include an oxide;

FIG. 5B depicts a cross sectional view of the structure of FIG. 4B afterapplication of a third sacrificial material which may include an oxide;

FIG. 6A depicts a cross sectional view of the structure of FIG. 5A afterremoval of the exposed hardmask material, and formation of an uppersource drain junction;

FIG. 6B depicts a cross sectional view of the structure of FIG. 5B afterremoval of the exposed hardmask material, and deposition of an uppersource drain junction;

FIG. 7A depicts a cross sectional view of the structure of FIG. 6A afterapplication of a cap, which may be composed of a self aligned contactnitride above the upper source drain junction;

FIG. 7B depicts a cross sectional view of the structure of FIG. 6B afterapplication of a cap, which may be composed of a self aligned contactnitride above the upper source drain junction;

FIG. 8A depicts a cross sectional view of the structure of FIG. 7A afterremoval of the third sacrificial material;

FIG. 8B depicts a cross sectional view of the structure of FIG. 7B afterremoval of the third sacrificial material;

FIG. 9A depicts a cross sectional view of the structure of FIG. 8A afteradding a top spacer by means which may include deposition consisting ofa material that may include SiN;

FIG. 9B depicts a cross sectional view of the structure of FIG. 8B afteradding a top spacer by means which may include deposition consisting ofa material that may include SiN;

FIG. 10A depicts a cross sectional view of the structure of FIG. 9Aafter removal of the second sacrificial material;

FIG. 10B depicts a cross sectional view of the structure of FIG. 9Bafter removal of the second sacrificial material;

FIG. 11A depicts a cross sectional view of the structure of FIG. 10Aafter removal of the first sacrificial material;

FIG. 11B depicts a cross sectional view of the structure of FIG. 10Bafter removal of the first sacrificial material;

FIG. 12A depicts a cross sectional view of the structure of FIG. 11Aafter application of a material layer through means such as chemicaldeposition wherein the material contains the property of having a highdielectric constant;

FIG. 12B depicts a cross sectional view of the structure of FIG. 11Bafter application of a material layer through means such as chemicaldeposition wherein the material contains the property of having a highdielectric constant;

FIG. 13A depicts a cross sectional view of the structure of FIG. 12Aafter deposition of a work function metal layer;

FIG. 13B depicts a cross sectional view of the structure of FIG. 12Bafter deposition of a work function metal layer;

FIG. 14A depicts a cross sectional view of the structure of FIG. 13Aafter deposition of a gate metal;

FIG. 14B depicts a cross sectional view of the structure of FIG. 13Bafter deposition of a gate metal;

FIG. 15A depicts a cross sectional view of the structure of FIG. 14Aafter removal of the gate metal except for the portions located underthe top spacer and above the bottom spacer;

FIG. 15B depicts a cross sectional view of the structure of FIG. 14Bafter removal of the gate metal except for the portions located underthe top spacer and above the bottom spacer;

FIG. 16A depicts a cross sectional view of the structure of FIG. 15Aafter the high K dielectric layer is removed except for the portionslocated under the top spacer and above the bottom spacer;

FIG. 16B depicts a cross sectional view of the structure of FIG. 15Bafter the high K dielectric layer is removed except for the portionslocated under the top spacer and above the bottom spacer.

DETAILED DESCRIPTION OF THE INVENTION

Aspects of the present invention and certain features, advantages, anddetails thereof, are explained more fully below with reference to thenon-limiting examples illustrated in the accompanying drawings.Descriptions of well-known materials, fabrication tools, processingtechniques, etc., are omitted so as not to unnecessarily obscure theinvention in detail. It should be understood, however, that the detaileddescription and the specific examples, while indicating aspects of theinvention, are given by way of illustration only, and are not by way oflimitation. Various substitutions, modifications, additions, and/orarrangements, within the spirit and/or scope of the underlying inventiveconcepts will be apparent to those skilled in the art from thisdisclosure.

Approximating language, as used herein throughout the specification andclaims, may be applied to modify any quantitative representation thatcould permissibly vary without resulting in a change in the basicfunction to which it is related. Accordingly, a value modified by a termor terms, such as “about,” is not limited to the precise valuespecified. In some instances, the approximating language may correspondto the precision of an instrument for measuring the value.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprise” (andany form of comprise, such as “comprises” and “comprising”), “have” (andany form of have, such as “has” and “having”), “include (and any form ofinclude, such as “includes” and “including”)”, and “contain” (and anyform of contain, such as “contains” and “containing”) are open-endedlinking verbs. As a result, a method or device that “comprises,” “has,”“includes” or “contains” one or more steps or elements possesses thoseone or more steps or elements, but is not limited to possessing onlythose one or more steps or elements. Likewise, a step of a method or anelement of a device that “comprises,” “has,” “includes” or “contains”one or more features possesses those one or more features, but is notlimited to possessing only those one or more features. Furthermore, adevice or structure that is configured in a certain way is configured inat least that way, but may also be configured in ways that are notlisted.

As used herein, the terms “may” and “may be” indicate a possibility ofan occurrence within a set of circumstances; a possession of a specifiedproperty, characteristic or function; and/or qualify another verb byexpressing one or more of an ability, capability, or possibilityassociated with the qualified verb. Accordingly, usage of “may” and “maybe” indicates that a modified term is apparently appropriate, capable,or suitable for an indicated capacity, function, or usage, while takinginto account that in some circumstances the modified term may sometimesnot be appropriate, capable or suitable. For example, in somecircumstances, an event or capacity can be expected, while in othercircumstances the event or capacity cannot occur—this distinction iscaptured by the terms “may” and “may be.”

As used herein, “depositing” may include any now known or laterdeveloped techniques appropriate for the material to be depositedincluding but not limited to, for example: chemical vapor deposition(CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD),semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapidthermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reactionprocessing CVD (LRPCVD), metal-organic CVD (MOCVD), sputteringdeposition, ion beam deposition, electron beam deposition, laserassisted deposition, thermal oxidation, thermal nitridation, spin-onmethods, physical vapor deposition (PVD), atomic layer deposition (ALD),chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.

Reference is made below to the drawings, which are not drawn to scalefor ease of understanding, wherein the same reference numbers are usedthroughout different figures designate the same or similar components.

In accordance with one aspect of this invention, the following describesa method for manufacturing a fin structure, wherein this fin structureincludes a fin with a sacrificial material above and/or adjacent to thefin. The fin structure also being above a substrate while being adjacentto a source or drain. The figures referenced are numbered and arelabeled (A) and (B) to show the corresponding method for a negativechannel field-effect transistor on the figures labeled with (A) and thecorresponding method for a positive channel field-effect transistor onthe figures labeled with (B).

Referring to FIG. 1A, a n-type vertical FIN field-effect-transistor(n-VFINFET) is initially fabricated in a conventional manner. Thestructure includes hardmask material 12 which is situated above thevertical FIN channel, and a bottom spacer 16, to a fin 14 and caninclude a bottom source/drain region 18 and a substrate 20. There mayalso be an isolation region (not shown) between adjacent devices 10 ifmore than one device is fabricated. Referring to FIG. 1B a structure ofa p-type VFINFET is fabricated in a conventional manner. The structureincludes a hardmask material 12, including but not limited to a nitridesuch as silicon nitride, which may be situated above and/or includedadjacent a bottom spacer 16 (typically a nitride material) to a fin 14and can include a bottom source/drain region 18 and an insulator region20. The n-VFINFET and p-VFINFET regions may be located on the samesemiconductor wafer, for example in different, yet adjacent areas of awafer separated by any distance that will not interfere with theoperation of a VFET device. The fin 14 may include semiconductormaterials, including but not limited to silicon, silicon germanium, andany III-V type materials. The bottom source/drain region 18 may includesilicon, silicon germanium, or any other semiconductor material, and maybe doped, often at high concentrations. The doping will vary for thedevice, but for an NFET it may be phosphorous doped and for a PFET itmay be boron doped. Additionally, the source/drain region 18 in FIG. 1Amay be different from the source/drain region 18 of FIG. 1B, and bothmay be doped differently. The substrate region 20 can include silicon,silicon germanium, and any type materials

Referring to FIG. 2A, a first sacrificial material 34 and a secondsacrificial material 36 are deposited onto the structure shown in FIG.1A. The first sacrificial material 34 may be in the form of a thin oxidedeposed on and surrounding the hardmask material 12 above the bottomspacer 16, the fin 14 and the bottom spacer 16 itself. The secondsacrificial material 36 may be an amorphous silicon layer and may bedeposited over and surrounding the first sacrificial material 34.Referring to FIG. 2B, the first sacrificial material 34 and secondsacrificial material 36 are deposited onto the structure shown in FIG.1A. The first sacrificial material 34 may be a thin oxide deposed on andsurrounding the hardmask material 12 above the bottom spacer 16, the fin14 and the bottom spacer 16 itself. The second sacrificial material 36which may be an amorphous silicon layer may be deposited over andsurrounding said first sacrificial material 34. First and Secondsacrificial material 34 and 36 may be deposited, for instance, by atomiclayer deposition (ALD), physical vapor deposition (PVD), or any otherchemical vapor depositions (CVD) capable of applying thin filmsconsistently.

Referring to FIG. 3A, the structure of FIG. 2A is planarized by, forexample, a chemical mechanical polishing (CMP) technique. Duringplanarization, the first sacrificial material 34 and the secondsacrificial material 36 is removed from a first portion 42, i.e., thetop of device 10, exposing the top section of the hardmask material 12.Then, as shown in FIG. 4A, a portion of the second sacrificial material36, adjacent to hardmask 12 and a top portion of fin 14, is removed by,for example, etching using any wet or dry etch techniques to recess thesecond sacrificial material 36 below a top surface of device 10.

FIG. 3B illustrates the planarization of the structure of FIG. 2B by,for example, CMP. During planarization, as described in reference toFIG. 3A, the first and second sacrificial material 34 and 36 is removedfrom a first portion 42. Then as shown in FIG. 4B, a portion of thesecond sacrificial material 36, adjacent to hardmask 12 and a topportion of fin 14, is removed by, for example, etching using any wet ordry etch techniques to recess the second sacrificial material 36 below atop surface of device 10.

Referring to FIG. 5A, a third sacrificial material 54, which may includean oxide material, is deposited by ALD, CVD, or PVD in some embodiments,in the region shown in FIG. 4A which has been etched to recess thesecond sacrificial material 36. Referring to FIG. 5B, third sacrificialmaterial 54 is similarly deposited on the positive channel.

Referring to FIG. 6A, the remaining hardmask material 12 is removed byselective etching processes to expose the fin 14. This can include anyetch that is selective for a nitride material, and may include plasmaetching. In its place, an upper source-drain 58 can be formed byselective epitaxy process, including but not limited to silicon andsilicon germanium. The material and doping of upper source-drain 58 maybe a different material for the n-VFINFET and p-VFINFET of FIGS. 6A and6B. For instance, the n-VFINFET (FIG. 6A) may include a heavilyphosphorus doped silicon material, and the p-VFINFET (FIG. 6B) may be aheavily boron doped SiGe material. The patterning processes to formseparate top S/D materials are not shown in detail here, because it isnot the main focus of this disclosure. As shown in FIG. 7A, a cap 62 isplaced above the upper source-drain junction 58. The cap 62 may becomposed of a nitride, which will assist in subsequent self-alignedcontact (SAC) etching to mask the upper source/drain junction 58 below.Similarly, referring to FIG. 6B, the hardmask material 12 is removed onthe p-VFINFET area by selective etching, to expose the fin 14. In itsplace an upper source-drain junction 58 can be formed. As shown in FIG.7B, the nitride SAC cap 62 is also deposited above the uppersource-drain junction 58 of the pFET region.

Referring to FIG. 8A, what remains of the third sacrificial material 54is removed, for instance, by buffered hydrofluoric acid (BHF) oxideetch, from the structure of FIG. 7A. This may also remove the exposedportion of the first sacrificial material 34 below upper source/drainjunction 58 and above the second sacrificial material 36. Then, depictedin FIG. 9A, a spacer 66 may be deposited adjacent the nitride cap 62 andaround exposed source/drain region 58. Spacer 66 can be of the samematerial as nitride cap 62, and thus is shown as a single feature.Deposition can include any of CVD, PVD, and ALD. The Spacer 66 may thenbe etched back, if necessary, so as not to cover the entirety of thesecond sacrificial material 36. The spacer 66 is deposited over andsurrounding the upper source-drain junction 58. Similarly, referring toFIG. 8B, the third sacrificial material 54 may be removed from the pFETregions as well as described above. Thereafter, as shown in FIG. 9B,spacer 66 is deposited adjacent the pFET nitride cap 62 and uppersource-drain region 58, creating a single spacer 66 merging with thenitride cap 62.

Referring to FIG. 10A and 10B, the second sacrificial material 36 maythen be removed by wet etching, such as hot ammonia or tetra methylammonia hydroxide (TMAH). Then, as shown in FIG. 11A and 11B, the firstsacrificial material 34 may then be removed by, for example, selectiveoxide etching or any other suitable techniques such as wet dilutehydrofluoric (DHF) etching, or dry chemical oxide removal (COR) process.

Referring to FIG. 12A and 12B, a high K dielectric material isconformally deposited over the spacers 66, the fin 14 and the bottomspacer 16 on both the n-VFINFET and p-VFINFET regions. The high Kdielectric can include HfO₂, ZrO₂, Al₂O₃, TiO₂, Ta₂O₅, lanthanide oxidesand mixtures thereof, silicates and materials such as YSZ(yttria-stabilized zirconia), BST, BT, ST, and SBT. Then, as shown inFIG. 13A and 13B, a work function metal (WFM) layer 74 is conformallydeposited over the high K layer and remaining structure. The WFM layer74 can include a single-element metal, for instance cobalt, titanium,aluminum, or other metals alloys that will allow proper workfunction togive desired threshold voltage (Vt), such as TiN, TaN, TiC, TiAl, etc,and may be deposited, for instance, using ALD. Additionally, the WFMlayer 74 for n-VFINFET and p-VFINFET may be different, and can be formedby, e.g, depositing first WFM for both p-VFINFET and n-VFINFET first,followed by a lithography process to block the p-VFINVET region, andremove the first WFM layer from the n-VFINFET, followed by resist strip,and followed by second WFM deposition over both n-VFINFET and p-VFINFET.Thus, the WFM layer 74 for n and p-VFINFET could be different materialswhich also may have different thickness. Then, as depicted in FIG. 14Aand 14B, a gate metal 78, for example tungsten or any other suitablemetal typically used in a replacement metal gate (RMG) process, may bedeposited on and surrounding the WFM layer 74 using ALD or otherdeposition techniques.

Referring to FIG. 15A and 15B, the gate metal 78 and WFM layer 74 may beselectively removed from the sides of the structure, but remainingbetween the upper source/drain junction 58 and adjacent the fin 14 andin the recess between spacer 66. In some embodiments, the selectiveremoval includes RIE, wherein the high K dielectric 70 layer, in someembodiments hafnium oxide (HfO₂), acts like a mask and protects the restof the structure, essentially a gate that has been formed self-alignedto the top S/D region to the VFINFET device, from erosion. Finally, asshown in FIG. 16A and 16B, the exposed portions of the high K dielectriclayer 70 are then removed, leaving only a lining in the recessesadjacent the fins 14, forming a self-aligned RMG gate in device 10 forboth the n-VINFETside (FIG. 16A) and the p-VFINFET side (FIG. 16B).

Following these steps, device 10 may be further processed following aknown set of steps for conventional VFINFET device flow to form aconnecting wire to bottom S/D, gate, and top S/D, followed by aback-end-of build.

Thus, as described above, methods according to certain embodiments allowfor an RMG gate that has been self-aligned to a vertical fin using theabove patterning techniques. The whole high-k/metal gate formation isafter bottom and top S/D formation, thus, the high-k and WFM won't seeany thermal impact due to the thermal budget during S/D formation. Also,due to the unique shape of the structure, different metal gate 78materials can be used to vary the threshold voltage (Vt) without concernfor how to recess the different metals in order to define the gatelength, since the unique shape of the high K dielectric layer 70 allowsfor self-patterning. Additionally, in recessing the gate, this alsoallows for protection from any plasma damage to the gate during therecessing.

What is claimed is:
 1. An intermediate semiconductor structurecomprising a fin structure comprising a fin above a substrate adjacent abottom source or drain; a top source or drain located on the top of thefin; a top spacer located above and surrounding said top source or drainand adjacent a top portion of said fin; a self-aligned gate structurelocated below said top spacer and above a bottom spacer located abovesaid substrate and source or drain; and one or more work function layerslocated between said bottom spacer and side walls of said fin and topspacer.
 2. The intermediate semiconductor structure of claim 1, whereinthe top source or drain comprises a phosphorus doped silicon material ora boron doped SiGe material.
 3. The intermediate semiconductor structureof claim 1, wherein the top spacer and the bottom spacer each comprise anitride material.
 4. The intermediate semiconductor structure of claim1, wherein the self-aligned gate structure comprises a high-k dielectriclayer adjacent the fin, the one or more work function layers, and a gatemetal adjacent the one or more work function layers.
 5. The intermediatesemiconductor structure of claim 4, wherein the high-k dielectric layercomprises HfO₂, ZrO₂, Al₂O₃, TiO₂, Ta₂O₅, lanthanide oxides and mixturesthereof, silicates, YSZ (yttria-stabilized zirconia), BST, BT, ST, orSBT.
 6. The intermediate semiconductor structure of claim 4, wherein theone or more work function layers comprise cobalt, titanium, aluminum,TiN, TaN, TiC, or TiAl.
 7. The intermediate semiconductor structure ofclaim 4, wherein the gate metal comprises tungsten.
 8. The intermediatesemiconductor structure of claim 1, wherein the fin comprises a dopedsemiconductor material.
 9. The intermediate semiconductor structure ofclaim 8, wherein the structure is an NFET and the fin is doped withphosphorous.
 10. The intermediate semiconductor structure of claim 1,wherein the structure is a PFET and the fin is doped with boron.
 11. Theintermediate semiconductor structure of claim 8, wherein thesemiconductor material comprises a type material.
 12. The intermediatesemiconductor structure of claim 8, wherein the semiconductor materialcomprises silicon or silicon germanium.
 13. The intermediatesemiconductor structure of claim 1, wherein the bottom source or draincomprises silicon or silicon germanium.